1. Field of the Invention
The present invention relates to semiconductor technology. More particularly, the present invention relates to a method for forming quantum dots for fabricating of an ultrafine semiconductor device and a method for forming a gate using the quantum dots.
2. The Related Art
Along with the development of semiconductor devices that have both high-speed operation and increased mass storage capabilities, fabrication technologies have been developing in order to create semiconductor devices with improved integrity, reliability, and a response speed.
One example of a general semiconductor device is flash memory, which is comprised of a general gate comprising a tunneling dielectric layer formed on a substrate of the semiconductor device, a floating gate formed on the tunneling dielectric layer, an oxide-nitride-oxide (ONO) layer formed on the floating gate, and a control gate formed on the ONO layer. In the devices currently known in the art, the minimum vertical thickness of the general gate is limited, making it difficult to forming a channel in the above-structured general gate. Unfortunately, this limitation hinders integrity of the device. Moreover, the thickness requirements of the general gate structure cannot be applied to an embedded-type flash memory.
In order to alleviate these difficulties, silicon (Si) quantum dots have recently been suggested as a substitute for the floating gate. For example, FIG. 1 is a sectional view showing the structure of a general conventional gate currently known in the art which includes quantum dots. Referring to FIG. 1, an isolation layer 2 is formed on a semiconductor substrate 1 in order to define an active region and an inactive region of the semiconductor substrate 1. Next, an oxide is vapor-deposited on the whole surface of the semiconductor substrate 1, thereby forming a first gate dielectric layer 3, or tunneling dielectric layer. A second gate dielectric layer 4 is formed by vapor-depositing a nitride such as SiON onto the first gate dielectric layer 3. The second gate dielectric layer 4 includes an excess of Si atoms which easily bond with oxygen atoms in order to form a Si—O configuration. The second gate dielectric layer 4 is formed to be thicker than the layer which includes the quantum dots formed in a subsequent process.
In addition, a conductive metal layer (not shown) is deposited on the second gate and a thermal treatment is performed on the conductive metal layer. As a result of the thermal treatment, the Si atoms of the second gate dielectric layer 4 and metal atoms of the conductive metal layer (not shown) are moved close to each other, thereby forming quantum dots 6 on the second gate dielectric layer 4. Then, the conductive metal layer (not shown) is removed, and a gate electrode material 5 is deposited on the second gate dielectric 4 layer which includes the quantum dots 6.
Then, a gate pattern is formed by performing an etching process, and a source and a drain are formed at a lower part of the semiconductor substrate 1 at a location adjoining the gate. Thus, structuring of the gate of the semiconductor device is completed.
Moreover, although not described above, according to the conventional method, the dielectric layer having the quantum dots is insulated by a dielectric material, such as an oxide or nitride, and then a gate poly for a control gate is vapor-deposited.
In such structures, the quantum dots need to be formed in uniform sizes and at uniform intervals. This is difficult to do, however, since the conventional methods typically form the quantum dots by vapor-depositing an amorphous poly and using agglomeration by the thermal treatment process, making it difficult to achieve uniform intervals between the quantum dots.